This invention relates to integrated circuits, and specifically to a structure and method for providing electrostatic discharge protection for integrated circuits containing a salicide component.
Silicon based integrated circuits are susceptible to electrostatic discharge (ESD) damage, particularly in the situation where a user of a device containing an integrated circuit develops a static charge on their body and subsequently comes in contact with the device containing the integrated circuit. The electrostatic charge induced in a human body may produce a voltage on the order of 5,000 volts. As most integrated circuits operate at no higher than five volts, an electrostatic discharge from a human body can be a traumatic experience for the integrated circuit. One way to provide an integrated circuit with ESD protection is to build an integrated circuit on a substrate that is less susceptible to damage from ESD. The integrated circuit may be fabricated on bulk silicon substrates, silicon on insulator (SOI) substrates, or separation by implantation of oxygen (SIMOX) substrates.
Electrostatic Discharge (ESD) Protection is generally provided by the addition of a masking step during manufacture of an integrated circuit device to prevent silicidation of a drain region adjacent to the gate electrode. This technique, however, does not provide complete ESD protection, and requires additional steps, time, and expense in the manufacturing process.
A method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density (IDD) process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.
It is an object of the invention to provide a CMOS structure with robust ESD protection without using an additional mask.
Another object of the invention is to provide a method of making a robust ESD protected device using a minimal number of steps.